This application claims priority under 35 U.S.C. xc2xa7xc2xa7119 and/or 365 to 9904527-0 filed in Sweden on Dec. 10, 1999; the entire content of which is hereby incorporated by reference.
The present invention relates to an arrangement in a multilayered electronic circuit for radio frequency applications, as well as a method of manufacturing such a circuit and a RF-circuit comprising such an arrangement.
Multilayered RF-circuits are used more and more in communications technology and elsewhere. The reason for this is that they allow smaller circuits to be built. One process resulting in multilayered RF-circuits is the LTCC process, an abbreviation for Low Temperature Cofired Ceramics. This process generally involves steps as follows. First holes are punched in predetermined patterns in a number of substrates. The holes are filled with a conductive material. When the circuit is finished, this material forms vias, which provide for vertical transitions within the circuit. Then planar conductive patterns are printed on at least some of the substrates. The pattern may also include different passive and active components that are formed on the substrate. The planar conductive patterns provide horizontal transitions within the circuit. Then the substrates are stacked in a predetermined order and with a predetermined orientation. In a final step, they are fired at a relative low temperature (for instance 850xc2x0 C.) to form a solid circuit.
An LTCC circuit normally contains a number of transmission lines. These may be devised as microstrip lines, striplines or even coaxial lines. A microstrip line, for instance, then consists of a planar ground conductor extending in a first plane and a planar signal conductor extending parallel to the ground conductor in a second plane adjacent to the first plane. The ground conductor normally has a wider lateral extension in its plane than the signal conductor has.
When two microstrip transmission lines, extending in different sets of layers are to be interconnected, this is arranged by means of via conductors. Then a first via interconnects the respective planar ground conductors, while another via interconnects the respective planar signal conductors.
A problem with this kind of transition is that the capacitance per length unit between the signal conductor and the ground conductor often is lower in the transition region as compared to the horizontally extending transmission line parts. This results in reflections when a signal having a predetermined frequency is propagated in the transmission line towards the transition region. The transition, thus, is not matched and this limits the RF performance, e.g. bandwidth, of the circuit.
A solution to this problem is to add a compensating element in the transition. This may be arranged in the following manner. If, for instance, the respective ground conductors of two interconnected planar transmission lines are placed above their respective signal conductors, the via interconnecting the signal conductors will pass in the vicinity of one edge of the lower planar ground conductor. If a projection is arranged in this planar conductor, protruding towards the via, this will result in a higher capacitance between the ground conductor and the signal via. Thus, the average capacitance per length unit between the signal conductor and the ground conductor is increased. This results in a circuit with improved RF performance.
It should be noted, however, in this context that the tolerances of the relative positions of adjacent layers as well as the relative positions of a via hole pattern and a planar conductor pattern within one layer in an LTCC circuit are relatively large.
This causes a problem with the above-described compensation arrangement. If a small change from the ideal distance between the ground conductor and parts of the signal via exists, the capacitance between them will differ from the intended one. The relation between distance and capacitance is a non-linear one. A relatively small displacement, positioning a segment part of the via conductor a bit closer to the planar ground conductor may render the compensating capacitance far too large. This is likely to reduce the bandwidth of the circuit to such an extent that it is useless for the intended purposes. A transition designed to be fully compensated in the ideal position will therefore have a relatively low yield when produced, i.e. only a relatively small number of circuits in a batch of a given size will function properly. This, of course, makes the circuits very expensive.
A procedure to deal with this problem is to under-compensate the transition, i.e. to design a ground conductor which, in an ideal relative position between the conductor and the via, has a capacitance somewhat less than the optimal capacitance. This results in higher yield but smaller bandwidth. Thus, a trade-off between yield and RF performance, e.g. bandwidth, exists
The present invention seeks to diminish the aforementioned problems.
One object of the present invention is to provide a low cost multilayered RF-circuit.
Another object is to achieve a multilayered RF-circuit with improved bandwidth.
Yet another object of the present invention is to achieve a method for producing a multilayered RF-circuit with improved yield.
The above-mentioned objects are achieved by means of an arrangement in a multilayered circuit, a method for manufacturing such a circuit in accordance with the invention as described below and multilayered RF-circuit comprising a similar compensating arrangement.
It has been observed by the inventor, that in a circuit manufactured in an LTCC process, the tolerances of the relative positions of different planar conductors within one layer are very small (typically around 5-10 xcexcm) compared to the tolerances of the relative positions of adjacent layers (which are typically around 50-100 xcexcm). The same applies for the relative positions of individual via holes within the via hole pattern in one layer, which also have small tolerances (typically around 5-10 xcexcm). The manufacturing tolerances as regards position of the hole pattern vis-xc3xa1-vis the position of the planar conductor pattern within one layer, however, is comparable to the tolerances of the relative positions of adjacent layers.
In accordance with the invention, the compensation in a transition between two planar transmission lines is made more process tolerant by utilising this observation. In an arrangement in accordance with the invention a first planar conductor, which may for instance constitute ground conductor in a planar transmission line, is formed on a first substrate layer among a plurality of substrate layers forming a multilayered circuit. The circuit further comprises a first via hole, formed in the first substrate layer or in a substrate layer adjacent to the first substrate layer on the side of the first planar conductor. The first via hole is filled with a conductive material and may form a segment part of a signal via providing a transition between two transmission lines. The capacitive coupling between the conductive material in the first via hole and the first planar conductor is intended to be within a predetermined range. In accordance with the invention a second planar conductor, which may be called a compensating planar conductor, is formed between the first via hole and the first planar conductor, on the same side of the same substrate layer as the first planar conductor. The surfaces of the first and the compensating planar conductors are formed to be non-intersecting. The first and the compensating planar conductors are interconnected by means of a conductive material disposed in a second via hole, which is formed in the same substrate layer as the first via hole. The second via hole may be called a compensating via hole.
Assume that the first planar conductor constitutes a ground conductor in a planar transmission line and that the conductive material with which the first via hole is filled forms a segment part of a signal via conductor, which intersects the plane in which the first planar conductor extends at a distance from its nearest edge. In an ideal case, in an arrangement in a circuit as defined above, a certain capacitance, within an intended range, is achieved between the first and second planar conductors on one hand and the intersecting via on the other. The equivalent model in this situation may schematically be described as a single capacitance C. If during the manufacturing of the circuit the hole pattern in question is displaced from its ideal position so that a part of the intersecting via approaches the first conductor, the compensating structure changes as well. This is due to the fact that the compensating via hole also is displaced. At a certain displacement of the hole pattern, the conductive material of the compensating via hole ceases to be in contact with both the first and the compensating conductor. This changes the schematic equivalent model of the compensating structure into two capacitances connected in series. The resulting capacitance of two capacitances connected in series may be written as 1/(1/C1+1/C2). This serves to compensate for the displacement of the segment of the intersecting via. The capacitance between the intersecting via and the planar ground conductor may therefore still be within the intended predetermined range.
This results in a less expensive circuit, since its fault tolerant qualities provide higher yield in a given manufacturing process.
It also allows multilayered RF-circuits with improved bandwidth properties to be produced at a relatively low cost.
A corresponding method may be defined where, in a step when via holes are formed in a layer, a via hole being positioned as said compensating via hole is formed. In another step in accordance with the invention, wherein a conductor pattern is disposed on a layer, a conductor corresponding to the compensating planar conductor as mentioned above is formed.
This results in a manufacturing process producing multilayered RF-circuits with improved yield.
An arrangement in a multilayered electronic circuit for radio frequency applications in accordance with the invention is then characterised as it appears from claims 1 or 10.
A method of manufacturing such a circuit in accordance with the invention is then characterised as it appears from claim 7. A multilayered RF-circuit comprising a compensating arrangement is further characterised in claim 10.